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1 ? fn6306.0 isl8105, isl8105a 5v or 12v single synchronous buck pulse-width modulatio n (pwm) controller the isl8105 makes simple work out of implementing a complete control and protection scheme for a dc/dc stepdown converter driving n-channel mosfets in a synchronous buck topology. since it can work with either 5v or 12v supplies, this one ic can be used in a wide variety of applications within a system. the isl8105 integrates the control, gate driver s, output adjustment, monitoring and protection functions into a single 8 ld soic package. the isl8105 provides single feedback loop, voltage-mode control with fast transient resp onse. the output voltage can be precisely regulated to as low as 0.6v, with a maximum tolerance of 1.0% over temperature and line voltage variations. a selectable fixed frequency oscillator (isl8105 for 300khz; isl8105a for 600khz) reduces design complexity, while balancing typical application cost and efficiency. the error amplifier featur es a 20mhz gain-bandwidth product and 9v/ s slew rate which enables high converter bandwidth for fast transient performance. the resulting pwm duty cycles range from 0% to 100%. protection from overcurrent co nditions is provided by monitoring the r ds(on) of the lower mosfet to inhibit pwm operation appropriately. this approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. features ? operates from +5v or +12v supply voltage (for bias) - 1.0v to 12v v in input range - 0.6v to v in output range - integrated gate drivers use v cc (5v - 12v) - 0.6v internal reference; 1.0% tolerance ? simple single-loop control design - voltage-mode pwm control - drives n-channel mosfets ? fast transient response - high-bandwidth error amplifier - full 0% to 100% duty cycle ? lossless, programmable overcurrent protection - uses lower mosfet?s r ds(on) ? small converter size in 8 ld soic - 300khz or 600khz fixed frequency oscillator - fixed internal soft-start, capable into a pre-biased load - integrated boot diode - enable/shutdown function on comp/sd pin - output current sourcing and sinking ? pb-free plus anneal available (rohs compliant) applications ? power supplies for microprocessors or peripherals - pcs, embedded controllers, memory supplies - dsp and core communications processor supplies ? subsystem power supplies - pci, agp; graphics cards; digital tv - sstl-2 and ddr/ddr2/ddr3 sdram bus termination supply ? cable modems, set top boxes, and dsl modems ? industrial power supplies; general purpose supplies ? 5v or 12v-input dc/dc regulators ? low-voltage distributed power supplies ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl8105cbz (300khz) 8105cbz 0 to 70 8 ld soic m8.15 isl8105acbz (600khz) 8105acbz 0 to 70 8 ld soic m8.15 isl8105ibz (300khz) 8105ibz -40 to 85 8 ld soic m8.15 isl8105aibz (600khz) 8105aibz -40 to 85 8 ld soic m8.15 isl8105eval1 evaluation board add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-f ree soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. pinout isl8105 (soic) top view 5 6 8 7 4 3 2 1 ugate gnd phase fb vcc comp/sd boot lgate/ocset data sheet june 6, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6306.0 june 6, 2006 block diagram typical application + - + - + - oscillator inhibit pwm comparator error amp vcc pwm gnd fb comp/sd oc comparator gate control logic boot ugate phase 21.5 a fixed 300 (or 600)khz lgate/ocset vcc soft-start por and sample and hold d boot + - dis 0.4v internal regulator dis 0.6v to lgate/ocset 20 a 20k 5v int. 5v int. v cc +v o fb comp/sd ugate phase boot vcc gnd lgate/ocset 5 7 63 8 1 2 4 isl8105 r s r offset c i c f r f l out c boot c bulk c dcpl c hf c out v in 5v or 12v 1v-12v r ocset type ii compensation shown isl8105, isl8105a
3 fn6306.0 june 6, 2006 absolute maximum rati ngs thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 15v boot voltage, v boot . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 36v ugate voltage v ugate . . . . . . . . v phase - 0.3v to v boot + 0.3v lgate/ocset voltage, v lgate/ocset gnd - 0.3v to v cc + 0.3v phase voltage, v phase . . . . . . . . . .gnd - 0.3v to v boot + 0.3v upper driver supply voltage, v boot - v phase . . . . . . . . . . . . .15v clamp voltage, v boot - v cc . . . . . . . . . . . . . . . . . . . . . . . . . . .24v fb, comp/sd voltage. . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 6v esd classification, hbm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv esd classification, mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150v esd classification, cdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kv operating conditions supply voltage, v cc . . . . +5v 10%, +12v 20%, or 6.5v to 14.4v ambient temperature range isl8105c, isl8105ac . . . . . . . . . . . . . . . . . . . . . . . . 0c to 70c isl8105i, isl8105ai . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c junction temperature range. . . . . . . . . . . . . . . . . . .-40c to 125c thermal resistance ja (c/w) soic package (note 1) . . . . . . . . . . . . . . . . . . . . . . 95 maximum junction temperature (plastic package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. guaranteed by design; not production tested electrical specifications test conditions: v cc = 12v, t j = 0 to 85c, unless otherwise noted. parameter symbol test conditions min typ max units v cc supply current input bias supply current i vcc v cc = 12v; disabled 4 5.2 7 ma power-on reset rising v cc por threshold v por 3.9 4.1 4.3 v v cc por threshold hysteresis 0.30 0.35 0.40 v oscillator switching frequency f osc isl8105c 270 300 330 khz isl8105i 240 300 330 khz f osc isl8105ac 540 600 660 khz isl8105ai 510 600 660 khz ramp amplitude (note 2) v osc 1.5 v p-p reference reference voltage tolerance isl8105c -1.0 - +1.0 % isl8105i -1.5 - +1.5 % nominal reference voltage v ref 0.600 v error amplifier dc gain (note 2) gain - 96 - db gain-bandwidth product (note 2) gbwp - 20 - mhz slew rate (note 2) sr - 9 - v/ s gate drivers upper gate source impedance r ug-srch v cc = 14.5v; i = 50ma - 3.0 - upper gate sink impedance r ug-snkh v cc = 14.5v; i = 50ma - 2.7 - lower gate source impedance r lg-srch v cc = 14.5v; i = 50ma - 2.4 - lower gate sink impedance r lg-snkh v cc = 14.5v; i = 50ma - 2.0 - upper gate source impedance r ug-srcl v cc = 4.25v; i = 50ma - 3.5 - isl8105, isl8105a
4 fn6306.0 june 6, 2006 functional pin description v cc (pin 5) this pin provides the bias supp ly for the isl8105, as well as the lower mosfet?s gate, and the boot voltage for the upper mosfet?s gate. an internal 5v regulator will supply bias if v cc rises above 6.5v (but the lgate/ocset and boot will still be sourced by v cc ). connect a well- decoupled 5v or 12v supply to this pin. fb (pin 6) this pin is the inverting input of the internal error amplifier. use fb, in combination with the comp/sd pin, to compensate the voltage-control feedback loop of the converter. a resistor divider fr om the output to gnd is used to set the regulation voltage. gnd (pin 3) this pin represents the signal and power ground for the ic. tie this pin to the ground island/plane through the lowest impedance connection available. phase (pin 8) connect this pin to the source of the upper mosfet, and the drain of the lower mosfet. it is used as the sink for the ugate driver, and to monitor the voltage drop across the lower mosfet for overcurrent pr otection. this pin is also monitored by the adaptive shoot- through protection circuitry to determine when the upper mosfet has turned off. ugate (pin 2) connect this pin to the gate of upper mosfet; it provides the pwm-controlled gate drive. it is also monitored by the adaptive shoot-throug h protection circuitry to determine when the upper mosfet has turned off. boot (pin 1) this pin provides ground refe renced bias voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage suitable to drive an n-channel mosfet (equal to v cc minus the on-chip boot diode voltage drop), with respect to phase. comp/sd (pin 7) this is a multiplexed pin. during soft-start and normal converter operation, this pin represents t he output of the error amplifier. use comp/sd, in combination wi th the fb pin, to compensate the voltage-control feedback loop of the converter. pulling comp/sd low (v disable = 0.4v nominal) will shut-down (disable) the controller, which causes the oscillator to stop, the lgat e and ugate outputs to be held low, and the soft-start circuitry to re-arm. the external pull- down device will initially need to overcome up to 5ma of comp/sd output current. howeve r, once the ic is disabled, the comp output will also be disabled, so only a 20a current source will continue to draw current. when the pull-down device is released, the comp/sd pin will start to rise, at a rate determined by the 20a charging up the capacitance on the comp/sd pin. when the comp/sd pin rises above the v disable trip point, the isl8105 will begin a new initialization and soft-start cycle. lgate/ocset (pin 4) connect this pin to the gate of the lower mosfet; it provides the pwm-controlled gate drive (from v cc ). this pin is also monitored by the adaptive shoot-t hrough protection circuitry to determine when the lower mosfet has turned off. during a short period of time following power-on reset (por) or shut-down release, this pin is also used to determine the overcurrent threshold of the converter. connect a resistor (r ocset ) from this pin to gnd. see the overcurrent protection section for equations. an overcurrent trip cycles the so ft-start functi on, after two dummy soft-start time-outs. so me of the text describing the lgate function may leave off the ocset part of the name, when it is not relevant to the discussion. functional description initialization (por and ocp sampling) figure 1 shows a simplified timing diagram. the power-on- reset (por) function continually monitors the bias voltage at the v cc pin. once the rising por threshold is exceeded (v por ~4v nominal), the por function initiates the overcurrent protection (ocp) sample and hold operation (while comp/sd is ~1v). when the sampling is complete, v out begins the soft-start ramp. upper gate sink impedance r ug-snkl v cc = 4.25v; i = 50ma - 2.7 - lower gate source impedance r lg-srcl v cc = 4.25v; i = 50ma - 2.75 - lower gate sink impedance r lg-snkl v cc = 4.25v; i = 50ma - 2.1 - protection/disable ocset current source i ocset isl8105c; lgate/ocset = 0v 19.5 21.5 23.5 a isl8105i; lgate/ocset = 0v 18.0 21.5 23.5 a disable threshold (comp/sd pin) v disable 0.375 0.400 0.425 v electrical specifications test conditions: v cc = 12v, t j = 0 to 85c, unless otherwise noted. (continued) parameter symbol test conditions min typ max units isl8105, isl8105a
5 fn6306.0 june 6, 2006 if the comp/sd pin is held low during power-up, that will just delay the initialization until it is released, and the comp/sd voltage is above the v disable trip point. figure 2 shows a typical power-up sequence in more detail. the initialization starts at t0, when either v cc rises above v por , or the comp/sd pin is released (after por). the comp/sd will be pulled up by an internal 20a current source, but the timing will not begin until the comp/sd exceeds the v disable trip point (at t1). the external capacitance of the disabling device, as well as the compensation capacitors, will determine how quickly the 20a current source will charge the comp/sd pin. with typical values, it should add a small delay compared to the soft-start times. the comp/sd will conti nue to ramp to ~1v. from t1, there is a nominal 6. 8ms delay, which allows the v cc pin to exceed 6.5v (if rising up towards 12v), so that the internal bias regulator can turn on cleanly. at the same time, the lgate/ocset pin is in itialized, by disabl ing the lgate driver and drawing i ocset (nominal 21.5 a) through r ocset . this sets up a voltage that will represent the ocset trip point. at t2, there is a variable time period for the ocp sample and hold operation (0 to 3.4ms nominal; th e longer time occurs with the higher overcurrent setting). the sample and hold uses a digital counter and dac to save the voltage, so the stored value does not degrade, for as long as the v cc is above v por . see the overcurrent protection section for more details on the equations and variables. upon the completion of sample and hold at t3, the soft-start operat ion is initiated, and the output voltage ramps up between t4 and t5. soft-start and pre-biased outputs functionally, the soft-start intern ally ramps the re ference on the non-inverting terminal of the error amp from zero to 0.6v in a nominal 6.8ms the output voltage will thus follow the ramp, from zero to final value, in the same 6.8ms (the actual ramp seen on the v out will be less than the nominal time, due to some initialization timing, between t3 and t4). the ramp is created digitally, so there will be 64 small discrete steps. there is no simple way to change this ramp rate externally, and it is the same for either frequency version of the ic (300khz or 600khz). after an initialization period (t3 to t4), the error amplifier (comp/sd pin) is enabled, and begins to regulate the converter?s output voltage during soft-start. the oscillator?s triangular waveform is compared to the ramping error amplifier voltage. this generates phase pulses of increasing width that charge the output capacitors. when the internally generated soft-start voltage exceeds the reference voltage (0.6v), the soft- start is complete, and the output should be in regulation at the expected voltage. this method provides a rapid and controlled output voltage rise; there is no large inrush current charging the output capacitors. the entire start-up sequence from por typically takes up to 17ms; up to 10.2ms for the delay and ocp sample, and 6.8ms for the soft-start ramp. figure 3 shows the normal curve in blue; initialization begins at t0, and the output ramps bet ween t1 and t2. if the output is pre-biased to a voltage less than the expected value, as shown by the magenta curve, the isl8105 will detect that condition. neither mosfet will turn on until the soft-start ramp voltage exceeds the output; v out starts seamlessly ramping from there. if the out put is pre-biased to a voltage above the expected value, as in the red curve, neither mosfet will turn on until the end of the soft-start, at which time it will pull the output voltage down to the final value. any resistive load connected to t he output will help pull down the voltage (at the rc rate of the r of the load and the c of the output capacitance). gnd> comp/sd (1v/div) v out (1v/div) v cc (2v/div) ~4v por gnd> gnd> gnd> figure 1. por and soft-start operation figure 2. lgate/ocset and soft-start operation 0.4v comp/sd (0.25v/div) lgate/ocset (0.25v/div) lgate starts switching 3.4ms 3.4ms 0 - 3.4ms 6.8ms v out (0.5v/div) gnd> gnd> gnd> gnd> t0 t1 t2 t3 t4 t5 isl8105, isl8105a
6 fn6306.0 june 6, 2006 if the v in to the upper mosfet drain is from a different supply that comes up after v cc , the soft-start would go through its cycle, but with no output voltage ramp. when v in turns on, the output would follow the ramp of the v in (at close to 100% duty cycle, with comp/sd pin >4v), from zero up to the final expected voltage. if v in is too fast, there may be excessive inrush cu rrent charging the output capacitors (only the beginning of the ramp, from zero to v out matters here). if this is not acceptable, then consider changing the sequencing of the power supplies, or sharing the same supply, or adding sequencing logic to the comp/sd pin to delay the soft-start until the v in supply is ready (see input voltage considerations ). if the ic is disabled after soft-start (by pulling comp/sd pin low), and then enabled (by releasing the comp/sd pin), then the full initialization (including ocp sample) will take place. however, that there is no new ocp sampling during overcurrent retries. if the output is shorted to g nd during soft-start, the ocp will handle it, as described in the next section. overcurrent protection (ocp) the overcurrent function protects the converter from a shorted output by using the lower mosfet?s on-resistance, r ds(on) , to monitor the current. a resistor (r ocset ) programs the overcurrent trip level (see typi cal application diagram). this method enhances the converter?s efficiency and reduces cost by eliminating a current sensin g resistor. if overcurrent is detected, the output immediately shuts off, it cycles the soft- start function in a hiccup mode (2 dummy soft-start time-outs, then up to one real one) to pr ovide fault protection. if the shorted condition is not remov ed, this cycle will continue indefinitely. following por (and 6.8ms delay), the isl8105 initiates the overcurrent protection sample and hold operation. the lgate driver is disabled to allow an internal 21.5 a current source to develop a voltage across r ocset . the isl8105 samples this voltage (which is referenced to the gnd pin) at the lgate/ocset pin, and holds it in a counter and dac combination. this sampled voltage is held internally as the overcurrent set point, for as long as power is applied, or until a new sample is taken after coming out of a shut-down. the actual monitoring of the lower mosfet?s on-resistance starts 200ns (nominal) after the edge of the internal pwm logic signal (that creates the rising external lgate signal). this is done to allow the gate transition noise and ringing on the phase pin to settle out before monitoring. the monitoring ends when the internal pwm edge (and thus lgate) goes low. the ocp can be detected anywhere within the above window. if the regulator is running at high ugate duty cycles (around 75% for 600khz or 87% for 300khz operation), then the lgate pulse width may not be wide enough for the ocp to properly sample the r ds(on) . for those cases, if the lgate is too narrow (or not there at all) for 3 consecutive pulses, then the third pulse will be stre tched and/or inserted to the 425ns minimum width. this allows for ocp monitoring every third pulse under this condition. this can introduce a small pulse-width error on the output voltage, which will be corrected on the next pulse; and the output ripple voltage will have an unusual 3-clock pattern, which may look like jitter. if the ocp is disabled (by choosing a too-high value of r ocset , or no resistor at all), then the pulse stretching feature is also disabled. figure 4 illustrates the lgate pulse width stretching, as the width gets smaller. the overcurrent function will trip at a peak inductor current (i peak) determined by: where i ocset is the internal ocse t current source (21.5 a typical). the scale factor of 2 doubles the trip point of the mosfet voltage drop, compar ed to the setting on the figure 3. soft-start with pre-bias gnd> v out normal gnd> gnd> v out pre-biased v out over-charged t0 t1 t2 figure 4. lgate pulse stretching > 425 ns = 425 ns < 425 ns << 425 ns i peak 2i ocset xr ocset r ds on () ---------------------------------------------------------- - = isl8105, isl8105a
7 fn6306.0 june 6, 2006 r ocset resistor. the oc trip point varies in a system mainly due to the mosfet?s r ds(on) variations (over process, current and temperature). to avoid overcurrent tripping in the normal operating load range, find the r ocset resistor from the equation above with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine i peak for , where i is the output inductor ripple current. for an equation for the ripple current see output inductor selection . the range of allowable voltages detected (2 * i ocset * r ocset ) is 0 to 475mv; but the practical range for typical mosfets is typically in the 20 to 120mv ballpark (500 to 3000 ). if the voltage drop across r ocset is set too low, that can cause almost continuous ocp tripping and retry. it would also be very sensitive to system noise and inrush current spikes, so it should be avoided. the maximum usable setting is around 0.2v across r ocset (0.4v across the mosfet); values above that might disable the protection. any voltage drop across r ocset that is greater than 0.3v (0.6v mosfet trip point) will disable the ocp. the preferred method to disable ocp is simply to remove the resistor; that will be detected that as no ocp. note that conditions during power-up or during a retry may look different than normal operation. during power-up in a 12v system, the ic starts operation just above 4v; if the supply ramp is slow, the soft-start ramp might be over well before 12v is reached. so with lower gate drive voltages, the r ds(on) of the mosfets will be higher during power-up, effectively lowering the ocp trip. in addition, the ripple current will likely be differen t at lower input voltage. another factor is the digital nat ure of the soft-start ramp. on each discrete voltage step, there is in effect a small load transient, and a current spik e to charge the output capacitors. the height of the current spike is not controlled; it is affected by the step size of the output, the value of the output capacitors, as well as the ic error amp compensation. so it is possible to trip the overcurrent with inrush current, in addition to the normal load and ripple considerations. figure 5 shows the output response during a retry of an output shorted to gnd. at time t0, the output has been turned off, due to sensing an overcurrent condition. there are two internal soft-start delay cycles (t1 and t2) to allow the mosfets to cool down, to keep the average power dissipation in retry at an acceptable level. at time t2, the output starts a normal soft-start cycle, and the output tries to ramp. if the short is still app lied, and the current reaches the ocset trip point any time during soft-start ramp period, the output will shut off, and return to time t0 for another delay cycle. the retry period is thus two dummy soft-start cycles plus one variable one (which depends on how long it takes to trip the sensor each time). figure 5 shows an example where the output gets about half-way up before shutting down; therefore, the retry (or hiccup) time will be around 17ms. the minimum should be nominally 13.6ms and the maximum 20.4ms. if the short condition is finally removed, the output should ramp up no rmally on the next t2 cycle. starting up into a shorted load looks the same as a retry into that same shorted load. in both cases, ocp is always enabled during soft-start; once it trips, it will go into retry (hiccup) mode. the retry cycle will always have two dummy time-outs, plus whatever fraction of the real soft-start time passes before the detection and shutoff; at that point, the logic immediately starts a new two dummy cycle time-out. i peak i out max () i () 2 ---------- + > figure 5. overcurrent retry operation 6.8ms 6.8ms 0 - 6.8ms 6.8ms t0 t1 t2 t0 v out (0.5v/div) internal soft-start ramp gnd> t1 isl8105, isl8105a
8 fn6306.0 june 6, 2006 output voltage selection the output voltage can be programmed to any level between the 0.6v internal reference, up to the v in supply. the isl8105 can run at near 100% duty cycle at zero load, but the r ds(on) of the upper mosfet will effectively limit it to something less as the load current increases. in addition, the ocp (if enabled) will also limit the maximum effective duty cycle. an external resistor divider is used to scale the output voltage relative to the internal reference voltage, and feed it back to the inverting input of the error amp. see the typical application schematic on page 2 for more detail; r s is the upper resistor; r offset (shortened to r o below) is the lower one. the recommended value for r s is 1 - 5k (1% for accuracy) and then r offset is chosen according to the equation below. since r s is part of the compensation circuit (see feedback compensation section), it is often easier to change r offset to change the output voltage; that way the compensation calculations do not need to be repeated. if v out = 0.6v, then r offset can be left open. output voltages less than 0.6v are not available. input voltage considerations the typical application diagram on page 2 shows a standard configuration where v cc is either 5v (10%) or 12v (20%); in each case, the gate drivers use the v cc voltage for lgate and boot/ugate. in addition, v cc is allowed to work anywhere from 6.5v up to the 14.4v maximum. the v cc range between 5.5v and 6.5v is not allowed for long-term reliability reasons, but transitions through it to voltages above 6.5v are acceptable. there is an internal 5v regulator for bias; it turns on between 5.5 and 6.5v; some of the delay after por is there to allow a typical power supply to ramp up past 6.5v before the soft- start ramps begins. this prevents a disturbance on the output, due to the internal regulator turning on or off. if the transition is slow (not a step change), the disturbance should be minimal. so while the recommendation is to not have the output enabled during the transition through this region, it may be acceptable. the user should monitor the output for their application, to see if there is any problem. the v in to the upper mosfet can share the same supply as v cc , but can also run off a separate supply or other sources, such as outputs of other regulators. if v cc powers up first, and the v in is not present by the time the initialization is done, then the soft-start will not be able to ramp the output, and the output will later follow part of the v in ramp when it is applied. if this is not desired, then change the sequencing of t he supplies, or use the comp/sd pin to disable v out until both supplies are ready. figure 6 shows a simple sequencer for this situation. if v cc powers up first, q1 will be off, and r3 pulling to v cc will turn q2 on, keeping the isl8105 in shut-down. when v in turns on, the resistor divider r1 and r2 determines when q1 turns on, which will turn off q2, and release the shut-down. if v in powers up first, q1 will be on , turning q2 off; so the isl8105 will start-up as soon as v cc comes up. the v disable trip point is 0.4v nominal, so a wide variety of nfet?s or npn?s or even some logic ic?s can be used as q1 or q2; but q2 must be low leakage when off (open-drain or open-collector) so as not to interfere with t he comp output. q2 should also be placed near the comp/sd pin. the v in range can be as low as ~1v (for v out as low as the 0.6v reference). it can be as high as 20v (for v out just below v in ). there are some restrictions for running high v in voltage. the first consideration for high v in is the maximum boot voltage of 36v. the v in (as seen on phase) plus v cc (boot voltage - minus the diode drop), plus any ringing (or other transients) on the boot pin must be less than 36v. if v in is 20v, that limits v cc plus ringing to 16v. the second consideration for high v in is the maximum (boot - v cc ) voltage; this must be less than 24v. since boot = v in + v cc + ringing, that reduces to (v in + ringing) must be <24v. so based on typical circuits, a 20v maximum v in is a good starting assumption; the user should verify the ringing in their particular application. another consideration for high v in is duty cycle. very low duty cycles (such as 20v in to 1.0v out, for 5% duty cycle) require component selection co mpatible with that choice (such as low r ds(on) lower mosfet, and a good lc output filter). at the other extreme (for example, 20v in to 12v out), the upper mosfet needs to be low r ds(on) . in addition, if the duty cycle gets too high, it can affect the overcurrent sample time. in all cases, the input and output capacitors and both mosfets must be rated for the voltages present. v out 0.6v r s r o + () r o --------------------------- ? = r o r s 0.6v ? v out 0.6v ? ---------------------------------- = figure 6. sequencer circuit r 2 v in r 1 r 3 v cc to comp/sd q 2 q 1 isl8105, isl8105a
9 fn6306.0 june 6, 2006 switching frequency the switching frequency is either a fixed 300 or 600khz, depending on the part number chosen (isl8105 is 300khz; isl8105a is 600khz; the generic name ?isl8105? may apply to either in the rest of this document, except when choosing the frequency). however, all of the other timing mentioned (por delay, ocp sample, soft-start, etc.) is independent of the clock frequency (unless otherwise noted). boot refresh in the event that the ugate is on for an extended period of time, the charge on the boot capacitor can start to sag, raising the r ds(on) of the upper mosfet. the isl8105 has a circuit that detects a long ugate on-time (nominal 100s), and forces the lgate to go high for one clock cycle, which will allow the boot capacitor some time to recharge. separately, the ocp circuit has an lgate pulse stretcher (to be sure the sample time is long enough), which can also help refresh the boot. but if ocp is disabled (no current sense resistor), the regular boot refresh circuit will still be active. current sinking the isl8105 incorporates a mosfet shoot-through protection method which allows a converter to sink current as well as source current. care should be exercised when designing a converter with the isl8105 when it is known that the converter may sink current. when the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. this means that the converter is boosting current into the v cc rail, which supplies the bias voltage to the isl8105. if there is nowhere for this current to go, such as to other distributed loads on the v cc rail, through a voltage limiting protection device, or other methods, the capacitance on the v cc bus will absorb the current. this situation will allow voltage level of the v cc rail to increase. if the vo ltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the isl8105, then the ic will experience an irreversible failure and the converter will no longer be operational. ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode. application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close toget her as possible, using ground plane construction or single point grounding. figure 7 shows the critical power components of the converter. to minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. the components shown should be located as close together as possible. please note that the capacitors c in and c o may each represent numerous physical capacitors. for best results, locate the isl8105 within 1 inch of the mosfets, q 1 and q 2 . the circuit traces for the mosfet gate and source connections from the isl8105 must be sized to handle up to 1a peak current. figure 8 shows the circuit traces that require additional layout consideration. use single point and ground plane construction for the circuits shown. minimize any leakage current paths on the comp/sd pin and locate the resistor, r oscet close to the comp/sd pin because the internal current source is only 20 a. provide local v cc decoupling between v cc and gnd pins. locate the capacitor, c boot as close as practical to the boot and phase pins. all components used for feedback compensation (not shown) should be located as close to the ic as practical. feedback compensation this section highlights the design consideration for a voltage- mode controller requiring external compensation. to address a broad range of applications, a type-3 feedback network is recommended, as shown in the top part of figure 9. l o c o lgate/ocset ugate phase q 1 q 2 v in v out return isl8105 c in load figure 7. printed circuit board power and ground planes or islands figure 8. printed circuit board small signal layout guidelines +v cc isl8105 lgate/ocset gnd vcc boot l o c o v out load q 1 q 2 phase +v in c boot c vcc r ocset isl8105, isl8105a
10 fn6306.0 june 6, 2006 figure 9 also highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the isl8105 circuit. the output voltage (v out ) is regulated to the reference voltage, v ref . the error amplifier output (comp pin voltage) is compared with the oscillator (osc) modified saw- tooth wave to provide a pulse-width modulated wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the outpu t filter (l and c). the output filter capacitor bank?s equivalent series resistance is represented by the series resistor e. the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis, l and d represent the channel inductance and its dcr, while c and e represent the total output capacitance and its equivalent series resistance. the compensation network consis ts of the error amplifier (internal to the isl8105) and the external r1-r3, c1-c3 components. the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45). phase margin is the difference between the closed loop phase at f 0db and 180. the equations that follow relate th e compensation network?s poles, zeros and gain to the components (r1, r2, r3, c1, c2, and c3) in figure 9. use the following guidelines for locating the poles and zeros of the compensation network: 4. select a value for r1 (1k to 5k , typically). calculate value for r2 for desired converter bandwidth (f 0 ). if setting the output voltage via an offset resistor connected to the fb pin, ro in figure 9, the design procedure can be followed as presented. 5. calculate c1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher t he quality factor of the output filter and/or the higher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 6. calculate c2 such that f p1 is placed at f ce . 7. calculate r3 such that f z2 is placed at f lc . calculate c3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the switching frequency. change the numerical factor to reflect desired placement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended a mathematical model is used to plot the loop response. check the loop gain against the error amplifier?s open-loop gain. verify phase margin results and adjust as necessary. the following equations describe the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ): figure 9. voltage-mode buck converter compensation design - + e/a vref comp c1 r2 r1 fb c2 r3 c3 l c v in pwm circuit half-bridge drive oscillator e external circuit isl8105 v out v osc d ugate lgate ro phase f lc 1 2 lc ? ? --------------------------- = f ce 1 2 ce ?? ----------------------- - = r2 v osc r1 f 0 ?? d max v in f lc ?? --------------------------------------------- = c1 1 2 r2 0.5 f lc ??? ----------------------------------------------- - = c2 c1 2 r2 c1 f ce 1 ? ??? --------------------------------------------------------- = r3 r1 f sw f lc ------------ 1 ? --------------------- - = c3 1 2 r3 0.7 f sw ??? ------------------------------------------------- = g mod f () d max v in ? v osc ----------------------------- - 1sf () ec ?? + 1sf () ed + () c ?? s 2 f () lc ?? ++ ---------------------------------------------------------------------------------------- ? = g fb f () 1sf () r2 c1 ?? + sf () r1 c1 c2 + () ?? ------------------------------------------------------ ? = 1sf () r1 r3 + () c3 ?? + 1sf () r3 c3 ?? + () 1sf () r2 c1 c2 ? c1 c2 + ---------------------- ?? ?? ?? + ?? ?? ? ---------------------------------------------------------------------------------------------------------------------------- - ? g cl f () g mod f () g fb f () ? = where s f () , 2 fj ?? = isl8105, isl8105a
11 fn6306.0 june 6, 2006 compensation break frequency equations figure 10 shows an asymptotic plot of the dc/dc converter?s gain vs. frequency. the actual modulator gain has a high gain peak dependent on the quality factor (q) of the output filter, which is not shown. using the above guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 against the capabilities of the error amplifier. the closed loop gain, g cl , is constructed on the log- log graph of figure 10 by adding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. a stable control loop has a gain crossing with close to a -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. the mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. when designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, f sw . this is just one method to calculate compensation components; there are variati ons of the above equations. the error amp is similar to that on other intersil regulators, so existing tools can be used here as well. special consideration is needed if t he size of a ceramic output capacitance in parallel with bulk capacitors gets too large; the calculation needs to model them both separately (attempting to combine two diff erent capacitors types into one composite component mode l may not work properly; a special tool may be needed; contact your local intersil person for assistance). component selection guidelines output capacitor selection an output capacitor is required to filter the output and supply the load transient current. t he filtering requirements are a function of the switching fr equency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by t he esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-es r capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr avai lable in larger case sizes. however, the equivalent seri es inductance (e sl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a sing le large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. th e inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: f z1 1 2 r2 c1 ?? ------------------------------- - = f z2 1 2 r1 r3 + () c3 ?? --------------------------------------------------- = f p1 1 2 r2 c1 c2 ? c1 c2 + ---------------------- ?? ---------------------------------------------- - = f p2 1 2 r3 c3 ?? ------------------------------- - = 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 10. asymptotic bode plot of converter gain closed loop gain 20 d max v ? in v osc --------------------------------- log 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl i = v in - v out fs x l v out v in v out = i x esr x isl8105, isl8105a
12 fn6306.0 june 6, 2006 increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time re quired to change the inductor current. given a sufficiently fast control loop design, the isl8105 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor cu rrent from an initial current value to the transient current le vel. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q 1 turns on. place the small ceramic capacitors phys ically close to the mosfets and between the drain of q 1 and the source of q 2 . the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rm s current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. for a through hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge current at power-up. some capacitor series available from reputable manufacturers are surge current tested. mosfet selection/considerations the isl8105 requires 2 n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor. the switching losses seen when sourcing curr ent will be different from the switching losses seen when sinking current. when sourcing current, the upper mosfet realizes most of the switching losses. the lower switch real izes most of the switching losses when the converter is sinking current (see the equations below). these equations assume linear voltage- current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower mosfet?s body diode. the gate-charge lo sses are dissipated by the isl8105 and don't heat the mosfets. however, large gate- charge increases the switching interval, t sw which increases the mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. when operating with a 12v power supply for v cc (or down to a minimum supply voltage of 6.5v), a wide variety of n- mosfets can be used. che ck the absolute maximum v gs rating for both mosfets; it needs to be above the highest v cc voltage allowed in the syst em; that usually means a 20v v gs rating (which typically correlates with a 30v v ds maximum rating). low threshold transistors (around 1v or below) are not recommended, for the reasons explained in the next paragraph. for 5v only operation, given t he reduced available gate bias voltage (5v), logic-level transistors should be used for both n-mosfets. look for r ds(on) ratings at 4.5v. caution should be exercised with devices exhibiting very low v gs(on) characteristics. the shoot-through protection t rise = l x i tran v in - v out t fall = l x i tran v out p lower = io 2 x r ds(on) x (1 - d) where: d is the duty cycle = v out / v in , t sw is the combined switch on and off time, and f s is the switching frequency. losses while sourcing current losses while sinking current p lower io 2 r ds on () 1d ? () 1 2 -- - io ? v in t sw f s + = p upper io 2 r ds on () d 1 2 -- - io ? v in t sw f s + = p upper = io 2 x r ds(on) x d isl8105, isl8105a
13 fn6306.0 june 6, 2006 present aboard the isl8105 may be circumvented by these mosfets if they have large parasitic impedences and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turn ed on. also avoid mosfets with excessive switching times; the circuitry is expecting transitions to occur in under 50ns or so. bootstrap considerations figure 11 shows the upper gate drive (boot pin) supplied by a bootstrap circuit from v cc . the boot capacitor, c boot , develops a floating supply voltage referenced to the phase pin. the supply is refreshed to a voltage of v cc less the boot diode drop (v d ) each time the lower mosfet, q 2 , turns on. check that the voltage rating of the capacitor is above the maximum v cc voltage in the system; a 16v rating should be sufficient for a 12v system. a value of 0.1f is typical for many systems driving single mosfets. if v cc is 12v, but v in is lower (such as 5v), then another option is to connect the boot pin to 12v, and remove the boot cap (although, you may want to add a local cap from boot to gnd). this will make the ugate v gs voltage equal to (12v - 5v = 7v). that should be high enough to drive most mosfets, and low enough to improve the efficiency slightly. do not leave the boot pin open, and try to get the same effect by driving boot through v cc and the internal diode; this path is not designed for the high current pulses that will result. for low v cc voltage applications where efficiency is very important, an external boot diode (in parallel with the internal one) may be considered. the external diode drop has to be lower than the internal one; the resulting higher v g-s of the upper fet will lower its r ds(on) . the modest gain in efficiency should be balanced against the extra cost and area of the external diode. for information on the application circuit, including a complete bill-of-materials and circuit board description, can be found in application note an1258 . +v cc isl8105 gnd lgate/ocset ugate phase boot vcc +v in v g-s v cc - v d v g-s v cc c boot q1 q2 + - figure 11. upper gate drive bootstrap vcc + v d - isl8105, isl8105a
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6306.0 june 6, 2006 isl8105, isl8105a small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

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